fn6798 rev 2.00 page 1 of 10 october 16, 2015 fn6798 rev 2.00 october 16, 2015 ISL89410, isl8941 1, isl89412 high speed, dual channel power mosfet drivers datasheet the ISL89410, isl89411, isl89412 ics are similar to the el7202, el7212, el7222 seri es but with greater vdd ratings. these are very high speed matched dual drivers capable of delivering peak currents of 2.0a into highly capacitive loads. the high speed performance is achieved by means of a proprietary tur bo-driver circuit that speeds up input stages by tapping the wider voltage swing at the output. improved speed and dri ve capability are enhanced by matched rise and fall delay times. these matched delays maintain the integrity of input-to-output pulse-widths to reduce timing errors and cl ock skew problems. this improved performance is a ccompanied by a 10-fold reduction in supply currents over bipolar drivers, yet without the delay time problems commo nly associated with cmos devices. dynamic switching losses are minimized with non-overlapped drive techniques. features ? industry standard driver replacement ? improved response times ? matched rise and fall times ? reduced clock skew ? low output impedance ? low input capacitance ? high noise immunity ? improved clocking rate ? low supply current ? wide operating voltage range ? pb-free available (rohs compliant) applications ? clock/line drivers ? ccd drivers ? ultra-sound transducer drivers ? power mosfet drivers ? switch mode power supplies ? class d switching amplifiers ? ultrasonic and rf generators ? pulsed circuits pin descriptions pinouts isl89411 (8 ld pdip, soic) top view ISL89410 (8 ld pdip, soic) top view isl89412 (8 ld pdip, soic) top view manufactured under u.s. patent nos. 5,334,883, #5,341,047 nc ina gnd inb 1 2 3 4 8 7 6 5 nc outa v+ outb inverting drivers nc ina gnd inb 1 2 3 4 8 7 6 5 nc outa v+ outb non-inverting drivers nc ina gnd inb 1 2 3 4 8 7 6 5 nc outa v+ outb complementary drivers symbol pin descriptions v + power voltage from 4.5v to 18v. gnd power voltage return ina, inb logic inputs. outa outa non-inverted ouput for ISL89410. inverted output for isl89411 and isl89412. outb outb non-inverted output for ISL89410 and isl89412. inverted output for isl89411. nc these pins must be left unconnected. ordering information part number part marking temp. range (c) package pkg. dwg. # ISL89410ipz (note) (no longer available, recommended replacement: ISL89410ibz) 89410 ipz -40 to +85 8 ld pdip** (pb-free) e8.3
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 2 of 10 october 16, 2015 ISL89410ibz (note) 89410 ibz -40 to +85 8 ld soic (pb-free) m8.15e ISL89410ibz-t13* (note) 89410 ibz -40 to +85 8 ld soic (tape and r eel) (pb-free) m8.15e isl89411ipz (note) isl 89411ipz -40 to +85 8 ld pdip** (pb-free) e8 .3 isl89411ibz (note) 89411 ibz -40 to +85 8 ld soic (pb-free) m8.15e isl89411ibz-t13* (note) 89411 ibz -40 to +85 8 ld soic (tape and r eel) (pb-free) m8.15e isl89412ipz (no longer available, recommended replacement: isl89412ibz) 89412 ipz -40 to +85 8 ld pdip** (pb-free) e8.3 isl89412ibz (note) 89412 ibz -40 to +85 8 ld soic (pb-free) m8.15e isl89412ibz-t13* (note) 89412 ibz -40 to +85 8 ld soic (tape and r eel) (pb-free) m8.15e *please refer to tb347 for det ails on reel specifications. **pb-free pdips can be used for through-hole wave solder proces sing only. they are not intended for use in reflow solder proce ssing applications note: these intersil pb-free plastic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information part number part marking temp. range (c) package pkg. dwg. #
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 3 of 10 october 16, 2015 absolute maximum ratings thermal information supply (v+ to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.0v input pins . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +0.3v above v+ combined peak output current. . . . . . . . . . . . . . . . . . . . . . . . . . .4a maximum recommended operating conditions recommended operating v+ range. . . . . . . . . . . . . . 4.5v t o 18.0v input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v+ operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c power dissipation 8 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mw 8 ld pdip* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mw storage temperature range . . . . . . . . . . . . . . . . . .-6 5c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-4 0c to +85c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through-hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications t a = +25c, v = 18v unless otherwise specified; parameters with m in and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits establ ished by characterization and are not production tested. parameter description test conditions min typ max units input v ih logic 1 input voltage 2.4 v i ih logic 1 input current @v+ 0.1 10 a v il logic 0 input voltage 0.8 v i il logic 0 input current @0v 0.1 10 a v hvs input hysteresis 0.3 v output r oh pull-up resistance i out = -100ma 3 6 ? r ol pull-down resistance i out = +100ma 4 6 ? i pk peak output current source 2 a sink 2 a i dc continuous output current source/sink 100 ma power supply i s power supply current inputs high/ISL89410 4.5 7.5 ma inputs high/isl89411 1 2.5 ma inputs high/isl89412 2.5 5.0 ma v s operating voltage 4.5 18 v ac electrical specifications t a = +25c, v = 18v unles s otherwise specified. parameter description test conditions min typ max units switching characteristics t r rise time (note 1) c l = 500pf 7.5 ns c l = 1000pf 10 20 ns t f fall time (note 1) c l = 500pf 10 ns c l = 1000pf 13 20 ns t d1 turn-on delay time (note 1) see timing table on page 4 18 25 ns t d2 turn-off delay time (note 1) seetiming table on page 4 20 25 ns note: 1. limits established by characte rization and are not production tested.
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 4 of 10 october 16, 2015 timing table standard test configuration simplified schematic t r t r t f t f t d2 t d1 10% 90% 10% 90% 0 5v input 2.5v inverted output non-inverted output 4.7f tan+ output 1000pf input v+ 46 7 2 3 + - v ref v+ input output input buffer reference and level shifter inverting buffer with hysteresis 2nd inverting buffer super inverter + -
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 5 of 10 october 16, 2015 typical performance curves figure 1. max power/derating curves figure 2. switch threshold vs supply voltage figure 3. input current vs voltage figure 4. peak drive vs supply voltage figure 5. quiescent supply current ISL89410 isl89411 isl89412
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 6 of 10 october 16, 2015 figure 6. on resistance vs supply voltage figure 7. average supply current vs voltage and frequency figure 8. average supply current vs capacitive load figure 9. rise/fall time vs load figure 10. rise/fall time vs supply voltage figure 11. propagation delay vs supply voltage typical performance curves (continued)
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 7 of 10 october 16, 2015 isl89411 macro model **** isl89411 model **** * input * | gnd * | | vsupply * | | | vout .subckt m89411 2 3 6 7 v1 12 3 1.6 r1 13 15 1k r2 14 15 5k r5 11 12 100 c1 15 3 43.3 pf d1 14 13 dmod x1 13 11 2 3 comp1 x2 16 12 15 3 comp1 sp 6 7 16 3 spmod sn 7 3 16 3 snmod g1 11 0 13 0 938 .model dmod d .model spmod vswitch ron3 roff2meg von1 voff1.5 .model snmod vswitch ron4 roff2meg von3 voff2 .ends m89411 figure 12. rise/fall time vs temperature figure 13. delay vs tempe rature typical performance curves (continued)
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 8 of 10 october 16, 2015 .subckt comp1 out inp inm vss e1 out vss table { (v(i np) v(inm))* 5000} (0,0) (3.2,3.2) rout out vss 10meg rinp inp vss 10meg rinm inm vss 10meg .ends comp1 application guidelines it is important to mi nimize inductance to the power fet by keeping the output drive current loop as short as possible. also, the decoupling capacitor, cq, should be a high quality ceramic capacitor wit h a q that should be a least 10x the gate q of the power fet. a ground pl ane under this circuit is also recommended. in applications where it is diffi cult to place the driver very close to the power fet (which may result with excessive parasitic inductance), it then may be nec essary to add an external gate resistor to dampen the inductive ring. if this resistor must be too large in value to be effect ive, then as an alternative, schottky diodes can be added to clamp the ring voltage to v+ or gnd. where high supply voltage operat ion is required (15v to 18v), input signals with a minimum of 3 .3v input drive is suggested and a minimum rise/fall time of 100ns. this is recommended to minimize the internal bias current power dissipation. excessive power dissipation i n the driver can result when driving highly capacitive fet ga tes at high frequencies. these gate power losses ar e defined by equation 1: where: p = power q c = charge of the power fet at v gs v gs = gate drive voltage (v+) f sw = switching frequency adding a gate resistor to the output of the driver will transfe r some of the driver dissipation to the resistor. another possibl e solution is to lower th e gate driver voltage which also lowers q c . about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support figure 14. recommended layout methods gnd v+ c q loop as short as possible c q should be as close as possible to the v+ and gnd pins figure 15. suggested configuration for driving inductive loads gnd v+ c q parasitic lead inductance p2q c v gs ? ? f sw ? = (eq. 1) revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change october 16, 2015 fn6798.2 updated ordering information table on page 1. added revision history and about intersil sections. updated pod mdp0027 to m8.15e.
ISL89410, isl89411, isl89412 fn6798 rev 2.00 page 9 of 10 october 16, 2015 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise s pecified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side . dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view a typical recomme nded land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view b
fn6798 rev 2.00 page 10 of 10 october 16, 2015 ISL89410, isl89411, isl89412 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
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